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Digital Osc.

Digital oscilloscope implemented in a FPGA.


Status: Done.

Date Comment
2006-10-30 Project created.


A digital oscilloscope implemented in a FPGA. A signal is sampled via the Audio CODEC and it's waveform is displayed on a CRT/LCD using the vga DAC on an Altera DE2 board ( This project was a part of the Industrial digital contruction course at Chalmers and has been developed by Johan Böhlin, Martin Johansson, Jonatan Åkerlind and Anders Palmér.


The DE2 audio ADC samples the unkown signal at 96kHz. A VHDL block read the sampled value when a certain trigger level occures and store the sampled value to memory. The trigger level, trigger edge and number of samples can be set by the user. A soft processor, NIOS2, read the samples, format it as a wave, adds user interface menus and create a framebuffer. The framebuffer is read by the vga-block which uses the onboard vga DAC to transform the framebuffer to a image on the CRT/LCD.

The altera DE2 board. The altera DE2 board.


Block layout. Block layout.


All hardware in VHDL. C for soft CPU.


A lot of sourcecode. Ask if interested. The report can be downloaded here.


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hardware/digitalosc.txt · Last modified: 2010/07/15 05:11 (external edit)