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Processor in FPGA

Five stage pipeline, 22 instructions processor.


Status: Done.

Date Comment
2007-01-22 Project created.


A five stage pipline, 32-bit processor implemented in a Xlinix XCV300. The processor supports 22 different innstructions with one or more instruction modes. The specification can be found here. This project was a part of the Computer architecture implementation course at Chalmers and has been developed by Johan Böhlin, Martin Johansson, Jonatan Åkerlind and Samuel Karlsson.


The processor is build up by several modules. Pc-control, memory access blocks, decoder, register file, and alu separated with pipline registers into five pipline stages. The processor runs at xxMhz and has a Texe/Cpi.. (still unkown).

Block layout Block layout.

Simple block layout Simple block layout.


All harwdare written in VHDL.


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hardware/processorfpga.txt · Last modified: 2010/07/15 05:11 (external edit)